Digital circuits, such as microprocessors and memories, typically use flip-flops as temporary storage devices. As digital circuits, particularly microprocessors and memories, operate at ever faster speeds, demand for faster flip-flops increases.
A flop-flip has two stable states and changes from one state to another with the application of a clock signal. The clock signal has a positive edge and a negative edge. The positive edge of the clock signal means that the clock signal is transitioning from a low voltage level to a high voltage level. The negative edge of the clock signal means that the clock signal is transitioning from a high voltage level to a low voltage level. The low voltage level represents a digital or logical zero value, while the high voltage level represents a digital or logical one value.
A pulsed flip-flop has one stable state and outputs a pulse if a data input signal has a predetermined voltage level in response to the positive edge of the clock signal. Referring to FIG. 1, one prior art pulsed flip-flop 20 outputs a pulse on the positive edge of the clock signal that is supplied on the clock node 22. To have the flip-flop 20 operate synchronously with respect to the negative edge of the clock signal, an inverter 24 inverts the clock signal supplied to the flip-flop 20. However, the inverter 24 increases circuit complexity and increases the amount of time required for the clock signal to propagate through the flip-flop circuitry.
In the prior art flip-flop 20, an input multiplexor 30 receives data input signals (d0, d1) at data nodes 32, 34, select input signals (select 0, select 1) at select nodes 36, 38 and the clock signal at the clock node 22. The input multiplexor 30 connects to an output pulse driver circuit 40. The data input signals, select input signals and the clock signal are not directly supplied to the output pulse driver circuit 40. The output pulse driver circuit 40 receives an evaluation (eval) signal from the input multiplexor 30 at node 42 and a complementary evaluation signal (eval.sub.-- c) at node 44. The output pulse driver circuit 40 outputs a pulse in response to the evaluation and the complementary evaluation signals. In addition, the output pulse driver circuit 40 supplies feedback signals, window and windowc to the input multiplexor 30 via NMOS transistors 46 and 48, respectively.
One of the data nodes 32, 34, supplies the data input signal, (d0, d1 to an inverter, 50, 52, respectively. One of the select nodes 36, 38, supplies the select input signal, select 0, select 1, to an inverter 54, 56, respectively.
The input multiplexor 30 has data select blocks 58, 60. The data select blocks 58, 60 are the same except that different signals are input; therefore, only the operation of data select block 58 will be described. In data select block 58, a NOR gate 62 receives the inverted select 0 and d0 signals from inverters 54 and 50, respectively. Another NOR gate 64 receives the inverted select 1 and d1 signals from inverters 56 and 52, respectively. The output of the NOR gates 62, 64 is supplied to the gates of NMOS transistors 66 and 68, respectively, which are connected in parallel and act as a pull-down circuit 70.
The clock signal is supplied to the gate of NMOS transistor 71. When the clock signal has a digital high value, NMOS transistor 71 will turn on and allow the transistor 66, 68 to act as a pull-down circuit which will cause the evaluation signal to have a digital low value under certain conditions. In particular, the evaluation signal will have a digital low value when:
the d0 and select 0 signals have a digital high value, PA1 the inverted clock signal at transistor 71 has a digital high value, and PA1 the window signal at the gate of transistor 46 has a digital high value.
The window signal is typically at a digital high value and transistor 46 is typically on. Because of the operation of the output pulse driver circuit 40, which will be explained below, the evaluation signal is precharged to a digital high.
The output pulse generator 40 generates output signals Q and Q, on output nodes 72 and 74, respectively. Typically, Q and Q have a digital low value. Either Q or Q will output a pulse when the selected data input signal has a digital high value. Q and Q will not output a pulse simultaneously.
To generate the Q signal, a pair of cross-coupled inverters 76, 78, acts as a latch to store the state of the evaluation signal, which is typically a digital high value. The evaluation signal is also supplied to an inverter 80 which outputs the Q signal on output node 72. When the evaluation signal has a digital high value, inverter 80 outputs a Q signal with a digital low value.
The window signal is generated by a NOR gate 81a based on the state of a scan enable signal from scan enable logic 81b and a feedback evaluation signal (fb.sub.-- eval) from the Q signal generation logic. In this description, the scan enable signal is disabled with a digital low value and the output of the scan enable logic 81b is also a digital low value which does not affect the operation of the circuit. The scan enable signal and logic are used to test the circuitry. The window signal is therefore responsive to the feed back evaluation signal. When the Q signal is a logical one, the feedback evaluation signal will also be a logical one value causing the window signal to have a logical zero and turning off transistor 46. When the Q signal is a logical zero, the feed back evaluation signal will be a logical zero causing the window signal to have a logical one value and turning on transistor 46.
Within the output pulse generator 40, a reset circuit also controls the state of the evaluation signal based on the state of the Q and Q signals. When the Q and Q signals have a digital low value, a NOR gate 82 outputs a digital high value to an inverter 84 which supplies a digital low value to NAND gate 86. The NAND gate 86 generates a n-reset signal with a digital high value. The gate of a PMOS transistor 88 receives the p-reset signal. The source and drain of the PMOS transistor 88 connect to V.sub.dd and the evaluation signal at node 42, respectively. Since the supply voltage, V.sub.dd, has a digital high value and the gate of the PMOS transistor 88 has a digital high value, PMOS transistor 88 remains inactive.
The p-reset signal is also supplied to another inverter 90 which generates an n-reset signal at node 92 which is supplied to the gate of another NMOS transistor 94. When the p-reset signal has a digital high value, NMOS transistor 94 remains inactive and does not affect the voltage level of the Q signal and the p-reset signal remains in this quiescent state.
A separate reset signal is supplied to NAND gate 86 to force the flip-flop to output Q and Q signals. This description assumes that the reset signal is a digital high value and therefore is inactive.
When the evaluation signal has a digital low value, the output pulse generator and the reset circuit become active and output a pulse. In particular, when the evaluation signal has a digital low value, the cross-coupled inverters 76, 78 latch the digital low value. Simultaneous with the latching of the digital low value, inverter 80 outputs a digital high value as the Q signal.
The digital high Q signal causes the reset circuit and p-reset signal to become active. The digital high Q signal causes the signal on node 45 (i.e., the window signal) to have a digital low value, thus turning off transistor 46 and effectively isolating the input multiplexor 30 from the output pulse generator 40.
The digital high Q signal on node 72 causes the NOR gate 82 to output a digital low value to inverter 84, which supplies a digital high value to NAND gate 86. Since both inputs of NAND gate 86 are at a digital high, the p-reset signal has a digital low value. PMOS transistor 88 receives the digital low p-reset signal, turns on and causes the evaluation signal to have a digital high value which flows through inverter 80 to output a digital low Q signal on node 72. The cross-coupled inverters 76, 78 latch the digital high value.
Meanwhile, also in response to the digital high Q signal, the p-reset signal causes inverter 90 to output a digital high value. In response, transistor 94 turns on and pulls the Q signal to a digital low value.
The generation of a Q signal on node 74 is the same as that for the Q signal described above, except that the complement of the data signals,d0 and d1, is used.
The prior art positive edge triggered flip-flop of FIG. 1 is complex. In addition, this prior art flip-flop has a relatively long propagation time. Including inverter 24, there are six gate delays between the negative edge of the clock signal and the positive edge of the Q signal's output pulse.
It would be desirable to provide a negative pulse edge triggered flip-flop with reduced circuit complexity and reduced propagation time. To further reduce circuit complexity, a negative pulse edge triggeredflip-flop which eliminates the need for a window signal is also desirable.